clock skew

DCM can synthesize the clock frequency, phase shift and eliminate clock skew, solving many clocking issues.

DCM具有频率综合 、 相移功能,能够消除时钟偏移, 解决很多系统中的时钟问题.

By reasonably using the special resources in FPGA, such as DCMs ( Digital Clock Manager) and BUFGMUXs ( global clock MUX buffer) and manually building up a proper clock circuit, the interference to timing caused by clock skew is mostly reduced.

通过合理使用DCM（数字时钟管理单元）和BUFG-MUX（全局时钟选择缓冲器）等FPGA的特殊资源，手动搭建时钟电路，可以尽可能地减少时钟偏差对电路时序的影响。

Using the techniques of standing wave and coupled oscillator, the skew and jitter in global clock networks could decrease dramatically.

使用驻波和耦合振荡器技术的全局时钟网可以显著的减少信号的偏斜和抖动。

Simply introduced the base flow for Clock Tree Synthesis, and described the file of timing constrains, and then introduced the analysis for skew and timing after Clock Tree Synthesis in detail.

简要介绍了时钟树综合的基本流程，并对时序文件的内容作了简要的描述。然后对时钟树综合后的时钟偏差和时序的分析做了详细的阐述。

The buffer insertion is hierarchically arranged, as to reduce the sensitivity of clock skew.

算法中的BUFFER定位是层次式的, 有利于减少时钟偏差敏感度.